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Source Aware Lithography Difficulty Estimator Disclosure Number: IPCOM000217123D
Publication Date: 2012-May-03
Document File: 5 page(s) / 100K

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The invention provides a way to assess the difficulty of a pattern without knowledge of the source based on the extraction of the relevant feature to cluster the different patterns according to the possible available sources. Optical lithography is a core business for IBM and significant improvement in reliability and yield results in a competitive advantage. Lithographic difficulty estimation is fundamental to many steps of the IC design process (e.g. source-mask optimization), and in the newest lithographic processes, (22nm and smaller), it can be a vital step is considered vital. In one embodiment, the invention results in a reduced representative subset of tiles of an original layout. By running this set rather than the whole layout through printability simulation or source-mask optimization reduces significantly the amount of time needed to process and identify difficult constructs. This step is one of the most time consuming in the whole silicon chip design workload, and thus far no viable solution to this problem (to our knowledge) exists.

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Source Aware Lithography Difficulty Estimator

    Known solutions to these problems and their drawbacks To the best of our knowledge, all current methods require up-front knowledge of the source. As the

source is typically jointly optimized with the mask for any new layout to overcome the physical limits of the technological process, this knowledge is not there from the start.

    Current efforts within IBM for an efficient lithography difficulty estimator are based on the extraction and the analysis of the coefficients of different transforms of the designed layout (e.g. Fourier coefficients, diffraction orders, discrete cosine transform).

    In contrast to these approaches the invention accounts for the variability of the source and it is not based on the designed layout but on the desired printed image on the resist. Namely, the invention detaches the analysis from a particular source and possible mask and estimates how difficult it would be to find a mask that prints a correct lithographic profile.

    The invention, while using some insight from [1], differs in the lack of up-front specified source.

1 Summary of Invention

    The present invention relates to the lithographic process in VLSI design. More specifically, it relates to an accurate estimation tiles within a layout that are hard or harder to print, without being constrained to a particular source or mask.

2 Technical Background

Here, we give an introduction to the lithographic process required for

understanding of the invention steps. These technical details in are primarily

well-known in the scientific literature of optical proximity correction and printability analysis. In fact, a more detailed description can be found in [1], but it is limited to the case where the source is known and thus also Ω is known.

Almost every silicon chip is printed these days by a lithographic process using

a 193nm light source. The result of the process is usually called a latent image,

which we name U(r), and represents the part of the resist which has been impressed by the light. It can be considered, to within an small approximation, equal to the obtained metal pattern. We define it by its Fourier series expansion,

where kmn is a vector in the Fourier domain, and r is a vector in the spatial domain.

    U(r) is the result of the convolution between the optical kernel, K(kmn), and the diffraction pattern of the mask M(kmn), which is the Fourier series expansion of

the mask itself, that is U(r) = K ∗ M(r) in the spatial domain, or F[U(r)] = K(kmn) · M(kmn), in the Fourier domain.

    In modern lithographic processes, e.g., 32nm or 22nm, the source and the mask are not known a priori. The only information is that of the designed layout,

which itself is an abstraction of the desired pattern on the wafer. Therefore, old


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techniques to determine the printability of a pattern and/or how difficult it is to print are no longer useful.

Figure 1: A graphical representation of a designed layout (the...