Surety is performing system maintenance this weekend. Electronic date stamps on new Prior Art Database disclosures may be delayed.
Browse Prior Art Database

System and Method to generate Intelligent Testcases to Validate the Speculative and Superscalar features of the High-End Microprocessor.

IP.com Disclosure Number: IPCOM000218616D
Publication Date: 2012-Jun-06
Document File: 7 page(s) / 82K

Publishing Venue

The IP.com Prior Art Database


The test generation proposed has an intelligent approach to integrate the numerous testcases generated out of the either pseudo random or constraint solving tools and make the test very efficient and realistic. The realistic testing can stress the speculative execution engine and the superscalar functionality of the processor in addition to the existing algorithms which stress numerous units of the processor. Most of the existing solutions don't take the program flow into consideration when dealing with validation. Most of the present generation tools generate testcases based on constraints which primarily stresses the functional units and cache memory of the processor. Current generation processors are becoming much more advanced and very speculative in nature. The validation needs to integrate the speculative nature to make the tests more realistic.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 52% of the total text.

Page 01 of 7

System and Method to generate Intelligent Testcases to Validate the Speculative and Superscalar features of the High -End Microprocessor.

The core idea of this approach is the speculative test generation module which takes the input test pattern from any of the existing test generators. Tools like Gpro, fpgen employ constraint solving methodology to generate intelligent testcases. The primary job of the speculative test generation module is to build branch sequences which will be looped through for various paths in the graph generated by the speculative test generation module. It takes the blocks of test

patterns from the available test pattern generated by the existing tools and maps it to numerous nodes in the graph generated by the speculative test generation module. The method also

provides a to do the execution of the testing, but other approaches like simulation based test approach can also be adopted without affecting the core idea.

The central idea revolves around taking a test pattern generated by a validation tool and converting in into a pattern interspersed with branch instructions such that the not-taken path of the branch falls through to the next instruction. The test pattern in sub-divided into a number of basic blocks represented as Bi, 0 < i < n, as shown in Fig 1. An intelligent branch insertion module transforms the test pattern into a pattern that stresses the speculative execution engine in a superscalar processor. The execution flow of the resulting pattern (red lines denote the fall through path and blue lines denote the taken path) is as shown in the right hand side of Fig 1. The starting node loads the context for the test pattern so as to ensure that we always start from a known execution context for the GPR/FPR/VR used by the test stream. The end node saves the final context into a separate memory space which is used to compare results across runs.


Page 02 of 7

Figure 1

In order to generate a speculative test pattern, the generic test pattern from the exerciser is taken as input into a mapping module that maps each basic block Bi into a destination block called as a node (ni).

By adjusting the start address of a node, it can be made to cross a sector or cacheline boundary. These configurations result in interesting micro-architectural scenarios where mispredicted speculative demand loads can collide with pre-fetch loads before being redirected out to another cacheline/sector due to a misprediction.

Each bigger node Ni, 0 < i < q, consists of 'm' contiguous smaller nodes nj 0 < j < m as shown in Fig 2. The red lines indicate that for each smaller node nj in a bigger node Ni, a not taken path falls through to the next sequential node...