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Method to Verify Long Chains in Scan and LSRL Modes Disclosure Number: IPCOM000223065D
Publication Date: 2012-Oct-31

Publishing Venue

The Prior Art Database


SoC’s usually have long chain modes for functional debug and for burn-in testing. In the platform long chain, simulations are very time consuming, so these modes are not verified with Verilog simulations. Typically, such simulation will take up to a month or more with large compute resources. Because long chain verification is not feasible within the design cycle, we have developed an alternative approach. We perform a simulation that is executed in much less time (1 day) and also enables the following: • Logic verification through ZERO DELAY SIMS. • Timing verification using SDF sims. • Verification of debug modes.(functional debug) • Verification of long chains, critical of burnin tests.