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Branch Instructions with Various Targets Disclosure Number: IPCOM000223127D
Publication Date: 2012-Nov-05
Document File: 1 page(s) / 38K

Publishing Venue

The Prior Art Database


The invention pertains to branch instructions that are capable of selecting the next (target) instruction to be executed from more than one location (e.g. from a set of four instructions). The invention permits programmers to build addresses of more than one target instruction that should be executed based on the outcome of the condition that a branch instruction checks.

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Branch Instructions with Various Targets

Disclosed is a method that will allow branch instruction(s) to select their target's next instruction from more than one location. This invention is an extension of the well-known hardware select statement.

    Branch instructions provide the flexibility of exercising different segments of a computer program. There are many different types of machine branch instruction available for different machine architectures. In general, all of such branch instructions check a branch instruction condition code and, based on the outcome, select the next instruction to be executed from one of two instructions; either the instruction located at the branch target or the instruction that sequentially follows the branch instruction.

     Although the outcome of checking branch instruction conditions can provide more than two outcomes, currently only one of two instructions can be executed after a branch instruction. This invention, which is effectively a multiple condition branch instruction, selects the next instruction to be executed from a set of four instructions (or targets), rather than two. The programmer would build the addresses for the potential targets either in registers or in storage locations (similar to what is done for branch instructions). Since many registers would be required, the programmer would also need to establish/populate a table that would provide for the mapping of registers to different branch instructions.