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Method for Parallel Processing of Redundant Via Creation Disclosure Number: IPCOM000225766D
Publication Date: 2013-Mar-04
Document File: 2 page(s) / 58K

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Redundant vias are used to help improve the manufacturability of integrated circuits (semiconductor chips). Due to the very large number of single vias in designs today (tens of millions) it can take many hours, possibly days, to test each single via in a design and determine if a redundant via can replace it. The method of the invention permits the testing of each individual via to be split up into an unlimited number of pieces and run in parallel.

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Method for Parallel Processing of Redundant Via Creation

An integrated circuit chip comprises a number of active transistors, as well as resistors, capacitors, and inductors. These components are electrically coupled by interconnection conductors, or wires, to create a desired function on the chip.

The interconnection was often accomplished on two layers of wiring. Inter-level conductors, called vias, were used to electrically couple a signal on one wiring layer to another wiring layer. On the chip, one layer of wiring would have predominately horizontal wiring; the other layer would have predominately vertical wiring. For example, if an interconnection required that a signal be routed vertically 100 units and horizontally 45 units, a routing program or a graphics technician would route the signal 100 units on a layer predominantly used for vertical wiring, and 45 units on a second layer which was devoted primarily to horizontal wiring. The program or technician would complete the electrical path by placing a via at the intersection where the signal wire on the upper wiring layer is physically under the signal wire on the lower layer of wiring.

As integrated circuit manufacturing advanced, most chips now have six or more layers of wiring. Vias are still used to couple signal wire portions on different layers of wiring. Most chips, today, may have over 400,000 signals and over 4,000,000 vias to interconnect the circuits.

Vias are physically very small, the area of a via being limited to the area defined by the conjunction of the signal wiring shapes on the two layers. For example, if the signal wires are 0.5 microns wide, a via would be 0.5 micron wide by 0.5 micron high, at most. In practice, the via might be smaller yet to allow for mis-registration of the via on the signal wires, or to allow for other process tolerances. The extremely small size of the vias increases the probability, given normal process defect densities and tolerances, that some of the vias on the chip have defects, and may be much more resistive than would be expected.

Delays in signals on the chip are introduced when the signal wiring is resistive or has resistive

portions. A logic circuit driving the si...