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Pillar via formation

IP.com Disclosure Number: IPCOM000226245D
Publication Date: 2013-Mar-25
Document File: 5 page(s) / 136K

Publishing Venue

The IP.com Prior Art Database


Vias are fabricated using damascene methods. This disclosure describes methods and structures to fabricate vias using a sacrificial pillar sub-etch process for either tight pitch on chip wiring or relaxed pitch super thick wiring placed above the last tight pitch wiring level to fabricate inductors or other super thick passive elements.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 100% of the total text.

Page 01 of 5

Pillar via formation

Post M1 or Mx processing, fabricate a pillar structure, preferably using PVD silicon over the wiring level, pattern it into a pillar with the same size as the final via dimensions, passivate it with planerized dielectic, and subsequently remove the pillar material and form vias.

- reverse taper the pillar to form a tapered final via cross-section
- fabricate super thick inductors or Cu pillars above the last wiring level on chip

Figure 1.1: A structure cross-section showing a pillar VIA formation.

Here follow three means of achieving this structure.

The first method begins below, with figure 2.1.


Page 02 of 5

Figure 2.1: A first sequence to process a wafer for pillar formation is outlined.

Alternatively, in Fig 2.2, is shown....


Page 03 of 5

Figure 2.2: A second sequence to achieving pillar formation is outlined.

Figure 2.3a: A third sequence to achieve pillar formation is shown.


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Figure 2.3b


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Figure 2.3c:

Figure 2.3d: