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IP.com Disclosure Number: IPCOM000226322D
Publication Date: 2013-Mar-27
Document File: 3 page(s) / 73K

Publishing Venue

The IP.com Prior Art Database


Disclosed is a method for taking a three-dimensional (3D) Backside silicon surface Very Large Scale Integration (VLSI) chip physical design and converting that surface into a two-dimensional (2D) equivalent framework. This is done by merging the Backside VLSI chip design with respective optical, wafer alignment, and electrical design cells. The method includes mirroring the merged design, which allows for front-to-back surface alignment in a 3D wafer build. Also included are validation checks for correct surface-to-surface connection in the original 3D design.

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Three-dimensional Very Large Scale Integration (3D VLSI) technology requires circuit design on the Wafer's Backside. A method is needed to place the VLSI design on the silicon wafer Backside or Grindside (GS), provide reticle alignment for multiple GS design layers, and subsequently mirror the GS design to account for backside or GS wafer surface to Frontside or Device side (DS) alignment.

This invention allows 3D Backside circuits to be aligned to Front Side (2D) circuits in a fully automated application. As it is appended to a 2D mask build, the method integrates 2D and 3D in a single application. Current methods for 3D Backside mask build require manual intervention with significant TAT
(Turn Around Time) and do not easily work for production. Through Silicon Via (TSV) size and material allows 2D Terminal metal litho tooling and mask build consideration.

With this invention, the terminal metal design methodology is extended to the Backside design on multiple design layers. A core feature of the methodology is
to merge the 3D reticle build design (not present in 2D terminal metal) and the VLSI chip design, and then mirror the merged Backside design such that
intra-wafer surface alignment is achieved. This results in software that can be expanded to include Multiple Grindside RDL (Redistribution Design Lines) design levels, Through Silicon Alignment methodology, and multiple strata.

The 3D Backside mask build is fully integrated...