Browse Prior Art Database

Abstraction of Dotted Multi-master Buses to a Single End Point Disclosure Number: IPCOM000230053D
Publication Date: 2013-Aug-15
Document File: 4 page(s) / 91K

Publishing Venue

The Prior Art Database


Disclosed is a method to contain the coordination of the buses within a lower level of the firmware stack.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 50% of the total text.

Page 01 of 4

Abstraction of Dotted Multi -

-master Buses to a Single End Point

master Buses to a Single End Point

In high-end servers, it is common to have independent but redundant Field Replaceable Units (FRUs). In some cases, these redundant FRUs master operations on external buses which connect to a single end device. For I2C buses, it is common to dot the buses coming from the redundant FRUs so that a single bus is connected to the end device. The result of this is that either redundant FRU can master the bus to the end point. The down side is that, if not managed properly, the redundant FRUs can attempt to master the buses at the same time causing errors. There are at least three possible solutions to this: 1) add an additional device in the path which switches between which FRU can drive the endpoint. 2) use multi-mastered I2C engines/buses so one FRU can detect the other mastering the end device without causing problems 3) expose the redundancy to the higher level firmware applications to coordinate such that they never drive the redundant buses at the same time. This disclosures proposes a fourth option to contain the coordination of the buses within a lower level of the firmware stack. The first three solutions mentioned in the abstract have deficiencies depending on the requirements and other implementations of the systems:

1) Adding an additional component in the middle of the I2C path to fence one master off creates a single point of failure in the path to the end device, defeating some of the redundancy benefits.

2) Multi-mastered buses require that each bus have its own I2C engine which monitors the bus at all times to determine if the redundant FRU is also attempting to master on the bus. This is a negative in designs where one I2C engine is switched between a large number of I2C buses to drive the requested device. The single engine is used to save space within the chip sourcing the buses.

3) Exposing the redundancy to higher levels of firmware is complicated by the fact that multiple devices may reside on the same bus and be accessed by unrelated firmware components. Requiring these components to interact to manage the redundancy adds additional complexity into the application design.

    As an alternative to these options, providing a lower layer of firmware which uses bus locking to prevent multiple FRUs from mastering the bus at the same time is proposed. This solution will also hide the redundancy from higher level firmware applications by managing the redundant connections and taking the appropriate locks based on the access path. This solution eliminates the need for an additional device in the bus path, allows a single engine to master multiple buses, and eliminates additional complexity in the higher level applications.

    To isolate the higher level applications from the redundancy of the multiple engines which can master a bus, a firmware layer called a Redundancy Encapsulation Layer (REL) is added, which the higher level...