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A novel single stack write driver circuit for high performance memories Disclosure Number: IPCOM000230809D
Publication Date: 2013-Sep-13
Document File: 3 page(s) / 40K

Publishing Venue

The Prior Art Database


In deep submicron technologies, it has become difficult to yield memories on chips without the use of assist techniques for reading and writing from memories [1]. Negative bitline boosting techniques have been introduced in the industry since long [2,3] to enhance writeability of the 6T SRAM cell. However, the circuits employed to incorporate boosting use multiple transistors in the stack to drive the bitline low. This slows down the write performance by taking a long time to pull the bitline to ground. The bitline can be boosted only after the bitline has reached ground, to gain maximum power and writeability efficiency. This paper presents a single stack driver to bring the bitline to ground with only a single transistor. This paper assumes practising knowledge of SRAM design. The reader may refer to [1] for a summary.

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A novel single stack write driver circuit for high performance memories


In the Current SRAM circuits, the Write driver is a three Nmos stack for pulling the bit-line to ground level before boosting the bit-line to a further low voltage. Two Nmos with Bit line select, data as gate signals and a ground transistor (for enabling boost, we need this transistor) comprise the three stack(Fig.1). Bit line select is column mux signal.

We need to ensure that the bit-line is at ground level before boosting happens for effective usage of write assist. A faster bit-line discharge would ensure a better margin before write assist happens.

In corners where write assist is not required, a faster bit-line discharge would enable faster writing into sram cell. If the sram cell is written faster, write margin increases or the cycle time can be reduced by the amount of time it is faster.

A single stack pull-down of the bit-line, if possible in implementation, would get the bit-line to ground level at a much faster rate than a three stack pull-down, and will give us the above two benefits.

Proposed Structure for improved performance

The circuit in Fig.2 shows the proposed structure. In comparison with Fig1, it can be seen that while transistors M1,M2,M3 of Fig1 are involved in pulling the bitline to ground( VSS), Fig2 employs only one transistor to pull bitline to ground (Driven by WTS Fig2). Fig3 shows the resulting sharp bitline fall which in turn gives scope for perfor...