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ASIC Bit error-rate (BER) Checker Disclosure Number: IPCOM000233807D
Publication Date: 2013-Dec-23
Document File: 7 page(s) / 692K

Publishing Venue

The Prior Art Database


This disclosure describe ASIC Bit error-rate (BER) Checker

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 100% of the total text.

Page 01 of 7


© 2012 Altera Corporation-Confidential

Page 02 of 7


BER checker is a component of Eye monitor

(Previous) Bit checker issues

New bit checker architecture

Control scheme

Position selection

Page 03 of 7

Eye monitor overview


Page 04 of 7

(Previous) Bit checker issues

Error not accurate

Can be optimized

Nbit adder needed in upper level

Reset should be handled carefully

Async counter may violate timing at higher speed


Page 05 of 7

New bit checker architecture

Cycle counter is 48bit

Enough for test 0.5E-15 BER (1 cycle == 2 UI)

When error counter saturate, it'll stop cycle counter automatically

Register IF between BER checker and upper logic

Page 06 of 7

Control scheme

Page 07 of 7

Position selection

For each PI code, there're one or two "good position" (sel_2nd can be 1/0)

Correlation between "PI code change" and "selection change"

May just need to check two position