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Single Controller Architecture for Hybrid DIMM Disclosure Number: IPCOM000234121D
Publication Date: 2014-Jan-13
Document File: 8 page(s) / 124K

Publishing Venue

The Prior Art Database


Disclosed is a single controller architecture for hybrid DIMM.

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Page 01 of 8

Single Controller Architecture for Hybrid DIMM

Server memory technology is evolving and one such proposed solution is the use of a unique single controller which supports DRAM, FLASH, and/or any other non-volatile memory. Addressed in this solution is the use of a single controller which takes care of different addressing types like byte-to-byte or page-to-page. In this solution, the host is agnostic to the DIMM's hybrid feature and only the lowest addressability is presented to the host. A wide variety of user scenarios are discussed for both WRITE and READ operations (see Figures 1 through 11 below).

Problem Statement:

No single controller for a Hybrid architecture having different addressing schemes.

Flash-backed DIMMs have separate controllers for FLASH and separate Memory controllers for DRAM.

Cases where there are single controllers are ones where the addressing type is same - byte-to-byte or page-to-page.

Probable decrease in the amount of background operation by simplifying the address
translation table (the advantage of having a single controller that acts as an MC or a flash controller based on mode).

Struggle with simplifying the address translation from page to byte and vice versa.

Proposed Solution:

The host is agnostic to the DIMM's hybrid feature. The lowest addressability is presented to the host.

For example if NVM1 is byte addressable and NVM2 is page addressable, then the host sees the DIMM as byte addressable.

Internally, the addresses are contiguous. The controller can distinguish the boundary between where NVM1's address ends and NVM2's address begins and vice versa.

During a READ, based on the address being accessed, a mode bit would toggle the firmware

between NVM1 mode and NVM2 mode. There is an internal buffer that is commonly used by both NVMs for caching data before presenting it to host.

A life-time counter is associated with DATA in the higher-endurance NVM. It gets

incremented whenever a fresh WRITE happens in the NVM. When the NVM runs out of space, the data with the highest life time (which could be considered cold) is then written into the lower-endurance NVM.

Further, in-order to reduce the stress on the higher-endurance NVM, the wear-leveling

algorithm will ensure that the lower-endurance NVM is an extension of the higher-endurance

NVM in terms of DATA movement.

Block Diagram: General Architecture


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• Condition 1 - Only one addressability visible to host - the one with higher granularity (e.g., byte vs page case, byte is chosen)

• Condition 2 - Writes always goes to the NVM with higher endurance


The different addressability is handled by considering contiguous memory space. Consider

NVM1 to be byte addressable and NVM2 to be page addressable with a 4k page size.

The controller considers the addresses in NVM2 to be in increments of 4k bytes. W...