Circuit and Method for Clocking High Performance Internally Double-Clocked Memory
Publication Date: 2014-Jan-20
The IP.com Prior Art Database
A circuit and method is disclosed for clocking high performance internally double-clocked memory. The circuit and method provides an optimum delay between two internally generated cycles at worst case application while maintaining robust operating margins at fast corners.
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Circuit and Method for Clocking High Performance Internally Double -
Disclosed is circuit and method for clocking high performance internally double-clocked memory. The circuit and method provides a serial delay chain to generate internal clocks as illustrated in fig. 1. As illustrated, a 1st active cycle is timed by a bitcell control circuit. Further, the 1st to 2nd active cycle is separated by delay from a bias reference circuit. In addition, the 2nd active cycle is timed by another bitcell control circuit.
Fig. 2 illustrates the cycle to cycle separation circuit.
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In accordance with the circuit and method disclosed herein, the bias reference is generated by a resistor and diode-connected NFET to generate a large difference in bias voltage across voltage and process. The bias reference circuit feeds a Schmitt trigger. As a result at fast process and/or high voltage, the capacitor is discharged with the NFET with reduced VGS, and, at slow process and/or low voltage, capacitor is discharged with the NFET with large VGS. Fig. 3 illustrates the concept of capacitor discharge.
Thus, the circuit and method disclosed herein assists in clocking high performance,
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internally double-clocked memory.