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Impedance calibration Disclosure Number: IPCOM000234790D
Publication Date: 2014-Feb-05
Document File: 4 page(s) / 670K

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The Prior Art Database


This article describes a procedure to calibrate the impedance of DDR transmitters to an external high-precision resistor. In previous impedance calibration schemes first the pullup branch of the output stage is calibrated to the external resistor. This is then followed by an internal pull-down calibration. With the existence of thinoxide output stages that use additional supplies such as vproth for the protection of thinoxide pfets, the conventional calibration scheme has drawbacks with respect to the mismatch across the chip. This article proposes a modified impedance calibration scheme based on applying the external high-precision resistor for the calibration of the pull-down branch followed by local pull-up calibrations. By doing so the vproth mismatches are cancelled by the impedance calibration, which is an advantage over the previously applied calibration scheme.

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Impedance calibration

Local Impedance Calibration


    This article is related to the impedance calibration scheme of double data rate (DDR) memory links. With the change of DDR memory links from thick-oxide to thin-oxide output stages, a higher number of supply and biasing voltages need to be considered for the impedance calibration.

    The currently applied Z-cal scheme is shown in Fig. 1. The pullup and pulldown branch in the output stage have protection nfets and pfets, which receive the protection biasing voltage VDD for the nfets and VPROTH for the pfets. The protection fets are required to protect the remaining fets in the transistor stack from an overvoltage since the output stage supply VDDR is typically higher than the reliability voltage VMAX of thin-oxide devices (e.g. VDDR=1.5V, VMAX=1.1V). The advantage of thin-oxide fets is the smaller power consumption, which is due to the smaller parasitics.

    The impedance calibration for memory links is proposed in the JEDEC standard "DDR3 SDRAM Standard; JESD79-3D, Sep. 2009". It is based on an external high-precision 240 ohm resistor. In previous product generations this external 240 ohm resistor has been applied as pull-down resistor to the output of the Z cal unit, which is a replica of the I/Os' output stage. In a currently designed memory hub chip (Centaur) there is one Z cal unit for approx. 700 I/Os.

State of the art

    In a first step the pullup branch of the Z cal unit is calibrated to the external 240 ohm resistor. This is performed by sweeping the impedance calibration vector until the output of the comparator that compares the Z cal output to VDDR/2 flips its logical state. At the trip point the pullup branch exactly matches 240ohm since the resistive voltage divider equals half of the supply voltage (240ohm/(Zup+240ohm)xVDDR=VDDR/2). In this example the pullup impedance calibration vector is called pvtpl, whereas pvt stands for Process-Voltage-T emperature and pl stands for pfet linear weights.

    In a second step the external pulldown resistor gets disconnected and the Z cal's pulldown becomes enabled, while the pullup branch remains enabled with


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calibrated pvtpl settings. In this second step the other calibration vector called pvtnl (for pvt nfet linear weights) is swept until the comparator flips its state, which means that the pulldown branch is calibrated to 240ohm (since the comparison level is VDDR/2 and the pullup is also 240ohm). Once the pullup and pulldown branches have been calibrated, the pvtnl- and pvtpl-vectors are distributed to the individual I/Os.

Fig. 1 State of the art Z cal scheme.

Drawbacks of existing solution

    This impedance calibration procedure has the following disadvantage: In contrast to conventional voltage-mode drivers thin-oxide high-swing drivers for memory links use a pullup branch that includes a protection pfet, which is biased from vproth (voltage protection high-side supply). For compatibility reasons with the already...