BI-TRIANGULAR REFINEMENT OF PILLAR GRID CELLS TO REDUCE WELL INTERSECTION DISCREPANCIES
Publication Date: 2014-Feb-20
The IP.com Prior Art Database
Certain reservoir simulation workflows may use multi-scale grid representation (e.g., dual scale grid representation). An example process can start with a coarse grid model. Subsequently a refinement may be employed to generate one or more finer representations of the reservoir. The grids might share a number of properties while varying in others. A feature that may be shared or preserved is placement of well intersections. This is the point where a well trace intersects a cell face. It may be desired for the measured depth on the well trace to correspond with the different grid resolutions. This problem might not be trivial due to the non-planar nature of the pillar grid cell faces and potentially numerous and/or ambiguous ways of interpreting the exact location. An example embodiment can solve this problem for the top and bottom cell face in pillar grid.
Bi-triangular refinement of pillar grid cells to reduce well intersection discrepancies
 An example embodiment of the present disclosure may include one or more of a method, computing device, computer-readable medium, and system for bi-triangular refinement of pillar grid cells to reduce well intersection discrepancies.
BRIEF DESCRIPTION OF THE DRAWINGS
 Implementations of various technologies will hereafter be described with reference to the accompanying drawings. It should be understood, however, that the accompanying drawings illustrate only the various implementations described herein and are not meant to limit the scope of various technologies described herein.
 Figure 1 illustrates a computer system into which implementations of various technologies and techniques described herein.
 Other figures illustrate various aspects of example embodiments of the present disclosure.
 Fig. 1 below shows components of an example of a computing system 100 and an example of a networked system 110.
 The system 100 includes one or more processors 102, memory and/or storage components 104, one or more input and/or output devices 106 and a bus 108. In an example embodiment, instructions may be stored in one or more computer-readable media (e.g., memory/storage components 104). Such instructions may be read by one or more processors (e.g., the processor(s) 102) via a communication bus (e.g., the bus 108), which may be wired or wireless. The one or more processors may execute such instructions to implement (wholly or in part) one or more attributes (e.g., as part of a method). A user may view output from and interact with a process via an I/O device (e.g., the device 106). In an example embodiment, a computer-readable medium may be a storage component such as a physical memory storage device, for example, a chip, a chip on a package, a memory card, etc. (e.g., a computer-readable storage medium).
 In an example embodiment, components may be distributed, such as in the network system 110. The network system 1410 includes components 122-1, 122-2, 122-3, . . . 122-N. For example, the components 122-1 may include the processor(s) 102 while the component(s) 122-3 may include memory accessible by the processor(s) 102. Further, the component(s) 102-2 may include an I/O device for display and optionally interaction with a method. The network may be or include the Internet, an intranet, a cellular network, a satellite network, etc.
 Although only a few example embodiments will be described in detail below, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the present disclosure.
 Although various methods, devices, systems, etc., have been described in language specific to structural features and/or methodological acts, it is to be understood that...