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Method to perform timing driven placement to satisfy boundary timing constraints Disclosure Number: IPCOM000235046D
Publication Date: 2014-Feb-25
Document File: 1 page(s) / 28K

Publishing Venue

The Prior Art Database


This paper proposes an elegant and effective way to guide the gates along the boundary timing paths to be placed closer to the PI/PO. This is a powerful method to improve timing of VLSI designs.

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Method to perform timing driven placement to satisfy boundary timing constraints

How to close the design with early or incomplete boundary timing constraints is an unsolved problem for current design closure process. Designers generally had bad boundary timing constraints and it drives all latches and boundary logics towards PI/PO, causing bad internal latch to latch timing, over buffering and layer assignment. Most of time, designers are aware of that the assertions may be bad and need fix later. Or they want to put more focus on latch to latch paths.

This invention presents several methods to solve timing driven latch placement (and gate placement) to satisfy the boundary timing constraints at all design stages. The main idea is to put latches that are logically connected to PI/PO close to PI/PO by attractions or other placement constraints, and then allow flexible boundary assertion adjustment and run timing driven placement. The advantage of this approach is to give the max flexibility for boundary constraints, reduce the over buffering and layer assignment for boundary paths, and still focus on internal latch to latch paths.

The algorithm works in the following order.

1. Perform logic netlist traverse with depth first search starting from PI and PO, find the first fixed objects connecting to PI/PO (such as port affinity buffers) and the first set of latches connecting to them. Group PI, PO (if there are no fixed objects between PI/PO and latches) and fixed objects into "boundary fixed points" category.