A Graph-Based Modeling Method for Register Coupling in Chip Functional Verification
Publication Date: 2014-Feb-26
The IP.com Prior Art Database
This disclosure proposes a register verification system and method use a uniform flatform with a graph-based modeling mechanism, predict behaviors of register couplings for functional verification. This disclosure projects the coupling of register fields in a logic design to directed graphs. The registers/fields are corresponding to vertices which connected by direct edge of their dependency. It ues a novel Orthogonal List Register Database to store flatten register field, not whole register. Coressponding field update engine can on the fly update register value/attribute/relationship according to register coupling in a uniform flow.
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--Based Modeling Method for Register Coupling in Chip Functional Verification
Based Modeling Method for Register Coupling in Chip Functional Verification DESCRIPTION
A quagmire of functional verification is how to accurately synchronize configuration register states when complicated couplings exist and DUT (Device under Test) behaves obscurely. This invention proposes a graph-based modeling mechanism to predict behaviors of register couplings for functional verification.
Design verification becomes more challenging with the increasing of chip complexity. Recent methodologies prefer abstract-level modeling to facilitate verification development systematically. In TLM (Transaction-Level Modeling) , the use of packaged transactions transcends RTL (Register Transfer Level) behavior in efficiency of development. TLM-based methodologies, i.e. OVM (Open Verification Methodology)  and UVM  (Universal Verification Methodology) have become prevalent in functional verification.
However, it becomes complex to verify the behaviors of registers (and its fields) along with the increasing complexity of chip logic. Recent methodologies adopted specialized approaches to manage registers. By modeling the behavior of memory and register contents in a design, RGM (Register and Memory Package)  provided built-in mechanisms for efficient verification and modeling. Inherited from its predecessor, UVM REG (UVM Register Layer Classes)
 provides an abstract solution to bridge from high-level programming to protocol-level access operation, and to integrate functional test.
The states of configuration registers are kept as a mirror of DUT, either to examine the correctness of registers' function or to serve checker, reference model and coverage. When the data or attribute in a configuration register is determined by condition rules which are related with other registers' state, we call it register coupling. In other words, we define coupling as a kind of dependency between a pair of configuration registers (Or a pair of their fields).
The phenomenon of register coupling pervasively exists in control logic designs such as controller andprocessor, thereby perplexing functional verification. However, register coupling is not well supported in current verification tools. Previous studies of registers' verification mainly focus on testbench building rather behavior modeling. N. Kim only presented an automatic method to codify register descriptions for SOC verification . Y. X. Zhang's work only optimizes structure reusability of register layer, but neglect detailed behavior of registers . On the other hand, even though there are some works used to try to model behaviors of registers, they are still immature or incomplete. E.g. the emulation of indirect register has been supported by RGM and REG, but both of them failed in achieving flexibility and scalability [4, 5]. C. Blank only solved conflict of register bin...