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Method and System for Optimizing Circuit Designs for Reducing Gate-Induced Drain Leakages (GIDL) Disclosure Number: IPCOM000235483D
Publication Date: 2014-Mar-04
Document File: 2 page(s) / 36K

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The Prior Art Database


A method and system is disclosed for optimizing circuit designs for reducing Gate-Induced Drain Leakages (GIDL).

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Method and System for Optimizing Circuit Designs for Reducing Gate - Leakages (



Disclosed is a method and system for optimizing circuit design for reducing Gate-Induced Drain Leakages (GIDL). The method and system reduces GIDL leakages in logic circuits by optimizing circuit designs and using Computer-Aided

Design (CAD) methodologies to intelligently substitute problematic devices with low level GIDL devices wherever necessary. The substitution of GIDL devices is done periodically using a pre-defined algorithm that works on one or more conditions of monitoring system-level node voltage probabilities and active vs. sleep-mode operations.

In accordance with the method and system, probabilistic idle-state node voltages (Vpgs,

Vpds) are computed for each n-Field effect transistor (nFET) in circuit based on probable combinations of system-level inputs during sleep-mode operation. Probabilistic idle-state node voltages are mathematically computed using the following formulae:

Vpgs = VDD * P(Vgs = VDD) + 0 * P(Vgs = 0)

Vpds = VDD * P(Vds = VDD) + 0 * P(Vds = 0).

Subsequently, if nFET GIDL is much greater than pFET GIDL , and the value of Vpgs is less than the value of Vpds, then low level GDIL devices are substituted in place of high level problematic GDIL devices. The algorithm calculates the values using conditions as stated below:

if nFET GIDL >> pFET GIDL then

• For each nFET in circuit

• If Vpgs < 0V + Vx and Vpds > VDD - Vy then

• Substitute wi...