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Replacement Metal Gate Poly Open Scheme Disclosure Number: IPCOM000235790D
Publication Date: 2014-Mar-25
Document File: 3 page(s) / 120K

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The Prior Art Database


Disclosed is a method to eliminate the variability of SiN HM thickness incoming to Reactive Ion Etching (RIE) between, as well as across, wafers.

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Replacement Metal Gate Poly Open Scheme

In the current Poly Open Chemical Mechanical Planarization (CMP) (POC) scheme, the SiN HM is removed at the end of the POC module. The Power-on-Reset (POR) integration scheme has the following steps:

1. Tetraethyl Orthosilicate (TEOS)/Furnace Chemical Vapor Deposition (FCVD) CMP stopping on SiN HM

2. FCVD recess using SiCONi. Process removes SiN

3. High Density Plasma (HDP) oxide dep. Process removes SiN

4. HDP oxide CMP. Process removes SiN

5. Reactive Ion Etching (RIE) SiN HM selective to oxide

6. Poly pull by RIE/Wets

The SiN HM thickness incoming to RIE varies wafer-to-wafer (w-t-w) as well as across wafer due to variability by SiCoNi recess, HDP deposition, and HDP CMP. This variability is carried by RIE and results in gate height variability

The described method eliminates this variability by removing SiN HM at the beginning of the POC module. The method removes SiN HM after TEOS/FCVD CMP. The SiN HM removed is fixed, and there is no variation w-t-w or within wafer.

Figure 1: Incoming to POC Bilayer HM: Oxide (~45nm) / SiN (~40nm)

Figure 2: Post TEOS/FCVD CMP Residual oxide of 200A left on top of HM SiN


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Figure 3: Siconi / COR etch of ~250A FCVD Oxide Expose all SiN 50A FCVD Recess

Figure 4: RIE HM Expose all Poly Gates Oxide above poly ~ 30nm


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Benefits: SiN HM Thickness removed is fixed w-t-w and within chip. Spacer Height variability is significantly reduced.

Figure 5: FCVD Recess / HDP...