Memory Architecture for Implementing Multiple Decode Schemes
Publication Date: 2014-Mar-28
The IP.com Prior Art Database
With increase in demand for lot of applications in all electronic gadgets, demand for internal storage memory with wider data and word depth is increasing. SRAM’s are preferred as storage cells because of its higher processing speed. SRAM macro is designed putting together array of 6T cells with some periphery logic to enable reading from the cell and writing into the cell. Periphery not scaling to the same percentage as SRAM cells made designing SRAM macros with wider bits and words area in-efficient. We implement larger data widths with lower column muxing at sense-amplifier and write driver. In this paper we present an architecture which uses higher column muxing scheme to realize lower column muxing scheme. Proposed architecture is better in area and either same or better with respect to global bitline switching power. We will discuss area and power comparison results using 32nm SOI SRAM Compiler. This architecture can be further extended to any array based design.