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Apparatus and Method to reduce peak power consumption while running ATPG patterns

IP.com Disclosure Number: IPCOM000235871D
Publication Date: 2014-Mar-28

Publishing Venue

The IP.com Prior Art Database


During ATPG test process, patterns are shifted in during a scan phase. During capture phase, a capture pulse is applied to excite functional paths and capture logic values in flops. Typically, all the flops of a design are pulsed at the same time, creating a very high power consumption in a chip. Multiple such patterns cause this situation many times during the course of running ATPG patterns. Power consumption during ATPG can be significantly higher compared to peak power consumption in functional mode. This can cause undesirable IR droop, failure of patterns leading to yield loss when the reason for failure is not an actual fault but IR droop caused by the pattern, and also potential damage and accelerated aging in the chip. Existing measures such as testing only a part of the design at a time can reduce peak power consumption, but have the disadvantages of increased test time because logic that could have been tested simultaneously are now tested separately, with scan and capture cycles to be done all over again across blocks. Existing methods also have alternative solutions, such as giving multiple capture pulses to the design, each pulse toggling only a limited part of the design. This falls under sequential ATPG. This is not efficient, even though common ATPG tools can generate patterns with this scheme. The number of patterns is very large, and meeting coverage targets is always a challenge, leading to high TAT and low coverage. Combinational patterns generate high coverage efficiently. But, they need all captures to happen at the same time, with a single capture pulse. There is a need to make combinational patterns work in a multiple capture pulse scenario so that only a part of the entire design would be pulsed at a time, reducing the peak power consumption significantly. The methos detailed here describes circuit design and the mathematical framework and algorithm to make a design work in a combinational ATPG mode, yet with multiple capture pulses, achieving high coverage and low peak power consumption, without sacrificing test time