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System Performance Improvement Using Staged Interrupt Handling

IP.com Disclosure Number: IPCOM000235873D
Publication Date: 2014-Mar-28

Publishing Venue

The IP.com Prior Art Database

Abstract

HW uses interrupt mechanism to inform Firmware about events happening on it. These interrupts are processed by Firmware at higher priority then other tasks. All events on HW are not of equal priority. These can be from just informational events to critical events. Generally HW provides priority information when it sends the interrupt to FW. This priority information is generally used by FW to decide the order in which these interrupts should be processed.The problem with existing approaches is that priority information of a interrupt is used only in context of interrupt preemption. Before raising interrupt on FW, No distinction is based upon the urgency for interrupt handling. There can be events which does not need immediate service from FW. Though these events are informational only, they can interrupt the high priority tasks running on FW. Also when FW is serving a low priority interrupt and high priority interrupt comes, even in preemptive interrupt handlers, the context saving time increases the response time for high priority interrupts.