Method and System for Connecting Through Substrate Vias (TSVs) to Thermal Via Crack-Stops in 3-Dimensional (3D) Die Stacking(s)
Publication Date: 2014-Jun-05
The IP.com Prior Art Database
A method and system is disclosed for connecting through substrate vias (TSVs) to thermal via crack-stops in 3-dimensional (3D) die stacking (s).
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Method and System for Connecting Through Substrate Vias ( Crack-
Disclosed is a method and system for connecting through substrate vias (TSVs) to thermal via crack-stops in 3-dimensional (3D) die stacking(s). The method and system utilizes TSVs in die stacking(s) in addition to the thermal via crack-stops, which relieves pressure due to thermal expansions. Thermal via crack-stops arranged in the form of arrays, carries heat away from 3D die stacking(s) installed in electrical devices. TSVs connected to thermal via crack-stops reduce thermal impact of printed circuit boards (PCB) in various electrical devices.
In accordance with the method and system, as shown in Figure 1, one or more TSVs are connected to the thermal via crack-stops to provide additional thermal ways for heat to escape from 3D die stack(s). For TSVs that are formed prior to memory dies (M1), these can be formed underneath the crack stop and therefore requires no additional circuit area on the die. Optionally, TSVs can also be arranged offset from crack-stops in 3D die stacking.
Figure 2, illustrates a cross sectional view of the 3D die stacking, where one or more TSVs and bond pad are arranged offset from the crack-stops.
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Figure 3, illustrates a cross sectional view of 3D die stacking, where one or more TSVs and bond pad a...