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Method and System for Verifying Field Programmable Gate Array Configuration Files Stored in NOR Flash Disclosure Number: IPCOM000237320D
Publication Date: 2014-Jun-13
Document File: 2 page(s) / 66K

Publishing Venue

The Prior Art Database


Disclosed is a method and system for verifying field programmable gate array configuration files stored in NOR flash memory at predetermined periodic intervals.

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Method and System for Verifying Field Programmable Gate Array Configuration Files Stored in NOR Flash

Configuration data for conventional field-programmable gate arrays (FPGAs) is often stored in a memory device external to the FPGA; e.g., a NOR Flash memory device. Such devices, while generally considered nonvolatile, may still lose data over extended periods of time. The data stored within the memory device is often not checked until it becomes necessary to download new configuration data to the memory device, such as when an upgrade or patch file is loaded. When errors arise in an FPGA's configuration memory, an FPGA reconfiguration operation may fail. At best, this will cause the configuration operation to revert to a "golden image". At worst, a golden image will either not be present or will also be corrupt, causing a complete failure of the configuration operation.

While it is now fairly common for error checking to be performed on FPGA configuration data as it is read from memory (as it enters the FPGA), this technique does not provide a mechanism for correcting the errors that are encountered. It is far more beneficial to implement error checking plus error correction, thereby allowing corrupt configuration data to be used and also possibly "repaired". Disclosed below is a method and system for verifying and correcting the data used to configure FPGA devices.

First, FPGA configuration data must be preprocessed (encoded) to add error correction information to the data before it is loaded into the external configuration memory. The resulting data is organized into "code words", with the characteristic that a particular

number of errors can be corrected within each code word. The maximum number of tolerable errors within each code word may be a fixed number (deterministic error correction), or it may be a variable number (probabilistic error correction). Regardless, the data is encoded in such a way that some number of errors within each code word can be corrected. In one scheme, an FPGA performs error correction on individual "code words" as it reads them from the external memory, producing error-free configuration data that is uses to configure itself. This technique, while it allows the use of corrupt configuration data, does not correct the data stored in the external configuration memory. If errors within the memory continue to grow, then the number of errors may exceed the capability of the chosen error correction algorithm. In an alternative scheme, the FPGA is configured with corrected data, after which it rewrites the corrected data (including additional coding information for future correction operations) ba...