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Delay configurable standard cell architectures with consistent footprints Disclosure Number: IPCOM000237374D
Publication Date: 2014-Jun-16

Publishing Venue

The Prior Art Database


Standard cell designing has been a prime activity in achieving the desired outcome from a technology. There has been a lot of innovation around the cell structures that has provided stability yet flexibility in cell usage for complex microcontrollers. This paper will presents yet another enhancement to standard cell designing that adds flexibility in the design closure. The proposed cell architecture is a modification to existing standard cell architecture that provides the same cell functionality but with delay re-configurability to achieve different delay requirements without having to change the cell footprint. The proposed cell has the following advantages, - It can be used for timing ECO’s without any cell addition. - No change in placement and routing. - Minimize last stage challenges to avoid placement density increase, routing changes, etc.