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Reuse of DFT Patterns in Board-Level Debug

IP.com Disclosure Number: IPCOM000237376D
Publication Date: 2014-Jun-16

Publishing Venue

The IP.com Prior Art Database

Abstract

This paper describe a design-for-debug method to diagnosis chip on board level with DFT(Design-For-Test) scan patterns that are totally re-used from patterns on Auto Test Equipment (ATE). The combination of hardware and software in this method can reuse original ATPG (Automatic Test Pattern Generation) patterns under multiple scan chains, in addition to the capability of new pattern generation.