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High-Speed Layout Technique that Meets Electromigration Targets Without Hurting Speed Targets

IP.com Disclosure Number: IPCOM000237507D
Publication Date: 2014-Jun-19
Document File: 4 page(s) / 96K

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The IP.com Prior Art Database


Described is a high-speed layout technique that meets electromigration targets without hurting speed targets.

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-Speed Layout Technique that Meets Electromigration Targets Without Hurting

   Speed Layout Technique that Meets Electromigration Targets Without Hurting Speed Targets

This layout technique solves the problem of high-speed circuits needing to meet electromigration requirements on wires. Extra power MOSFET dummies are added to spread out current for electromigration requirements, but only near the power supply connection. The signal connection only has one single shared MOSFET RX area to keep parasitic capacitance low. This technique helps meet electromigration requirements in the chip wires while helping to keep capacitance low in order to meet high-speed operation. The two goals oppose each other because, while adding extra wires to meet electromigration goals, one is also adding extra capacitance that slows down the circuit. As CMOS technology gets more advanced, the speed targets are increasing but the electromigration requirements for the new technologies are getting harder - they are decreasing.

    The schematic in Figure 1 below shows stacked CMOS devices. When the devices switch, the cross-over current from the PFET down through the NFET is large for high-speed circuits, which are designed to have large MOSFETs to meet the speed requirement (bigger devices help you go faster).

    The layout in Figure 2 below shows how to share the signals on the drains of the MOSFETs, left and right, to minimize capacitance on the signal net while allowing one to spread the...