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Enhancing performance by reducing CPU wait time

IP.com Disclosure Number: IPCOM000237623D
Publication Date: 2014-Jun-27
Document File: 2 page(s) / 192K

Publishing Venue

The IP.com Prior Art Database


This paper introduces a mechanism that enables users to enhance CPU performance by reducing its wait time.

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1.       Abstract

This paper introduces a mechanism that enables users to enhance CPU performance by reducing its wait time.

2.       Introduction

Generally in System on a Chip (SoCs), the CPU clock and data path clocks are asynchronous. In such cases as soon as the CPU starts a transaction, the data path asserts a wait signal to ensure that the data has been correctly acknowledged in the data path clock domain. Once that is done, the data path clears the wait signal, allowing the CPU to start the next transaction. Clearly the CPU has to wait for the wait signal to be de-asserted to start the next transaction. This affects the efficiency at which it can configure the number of registers in the data path. This situation worsens when the CPU clock is fast and the data path is slow as the de-assertion of the wait signal will be significantly slow.

3.       Implementation

The design technique is used to control the wait generation logic associated with the CPU when the CPU is writing or reading data from a domain that is asynchronous to its own clock.

We can see in the timing diagram that the CPU wait has to be asserted for 9 clock cycles. This is a huge performance loss when the CPU does not have to write back-to-back consecutive data - it still has to wait for 9 clock cycles to complete every transaction even if it intends to write/read a single byte.

Existing techniques immediately generate a wait signal on a read/write assertion.  We provided a circuit that enhances the logic so that the wait signal is only generated for back-to-back read/write events.

We take advantage of the fact that in an SoC, back-to-back transactions on a particular IP are unlikely and hence the number of wait cycles is drastically reduced and hence there is a significant improvement in efficiency.

A block diagram of the circuit used to implement the technique follows.

Block Details:

•          Write Buffer block buffers the write trans...