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Method and system for efficient page table allocation

IP.com Disclosure Number: IPCOM000238062D
Publication Date: 2014-Jul-30

Publishing Venue

The IP.com Prior Art Database

Abstract

In post-silicon functional validation, memory access component generates accesses through out all available virtual memory space. In modern systems virtual memory space is extremely large (at least 48 bits in the current designs). Straightforward allocation of radix translation tables for all available virtual space results in huge amount of space for translation tables themselves. The problem is especially challenging when amount of physical memory is limited while virtual space remains huge, for example when running cache-contained.