Method and System for Blending Performance Screen Ring Oscillators (PSRO) Model for Hardware Correlation
Publication Date: 2014-Aug-05
The IP.com Prior Art Database
A method and system is disclosed for blending Performance Screen Ring Oscillators (PSRO) model for hardware correlation.
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Method and System for Blending Performance Screen Ring Oscillators ( for Hardware Correlation
Disclosed is a method and system for adjusting a position of a data in a Variation
Aware Timing (VAT) plot for representing the performance of a particular path to be correlated. The adjustment is based on the Performance Screen Ring Oscillators (PSRO) readings of different PSROs in a chip. Subsequently, the adjustment is weights based on the percent of the path that is expected to correlate to each PSRO type.
In an embodiment, the method and system uses VAT methodology and blend PSRO measurements together from a delay more representative of the path in the IP to be correlated. The blending is based on the amount of Vt type in the logic path to be correlated.
In an exemplary scenario, the MVT PSRO count 80% of the delay and the UVT PSRO count 20% of the delay. Further, if the MVT PSRO indicates that the part in bin 8 of 16 and the UVT PSRO indicates that the part in bin 12 of 16, then the path is actually considered to be in bin 9 of 16 (8*8/10 + 12*2/10 = 8.8) for MHC purposes and the data is plotted accordingly.
Thus, the method and system allows much better model to hardware correlation without changing the PSROs or IP. Further, the method and system can be extended to blending circuit dependencies other than Vt type. For example, a PSRO that is dependent on metal resistance could be blended with a PSRO.