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Cascaded Through Silicon Connection Disclosure Number: IPCOM000238476D
Publication Date: 2014-Aug-27
Document File: 2 page(s) / 36K

Publishing Venue

The Prior Art Database


Disclosed is a method to create a cascaded through silicon connection.

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This is the abbreviated version, containing approximately 95% of the total text.

Page 01 of 2

Cascaded Through Silicon Connection

Large Through Silicon Vias (TSVs) occupy large Silicon (Si) areas, which cannot be used for active devices and Back End of Line (BEOL) wiring. Small diameter TSVs require ultra-thin Silicon handling (below 10um). TSV height defines the max Silicon chip thickness due to limitations in high aspect ratio TSV fill.

The solution is to use small size/pitch (e.g., below 500nm) front side TSV (TI), which extends from CA (contact level) in to Si by ~5-10um. Connect the TIs from the "thick" Silicon backside by large TSVs, 5-20um in diameter, up to ~100um in depth. This eliminates ultra-thin wafer handling required for a TI only approach. Keeping the small TI provides the benefit of Si real estate gain for active devices and access to all BEOL levels as wiring. Keeping the thick wafer process/integration has the benefit of using the backside large size TSVs. The approach provides access of multiple TIs by single large TSV from the back side if needed.

Example process flow:

1. Form active devices, form local device connections and CA module 2. 2) Form Front side small TSV (diameter less than 0.5um) depth in to Silicon 7-10um

Figure 1: Steps 1 and 2

3. From BEOL wiring levels, final passivation, finish front side processing

4. Back side grinding down to ~100um Si thickness

Figure 2: Steps 3 and 4


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5. From BEOL wiring levels, final passivation, finish front side processing

6. Back side grinding down to ~100um Si thickness