Browse Prior Art Database

Enhanced metal-only ECO methodology using repurposed GA-fill-compatible non-essential logic gates Disclosure Number: IPCOM000238959D
Publication Date: 2014-Sep-29
Document File: 5 page(s) / 129K

Publishing Venue

The Prior Art Database


An ECO methodology is described which relies on repurposed GA-fill-compatible non-essential logic gates. This methodology lets designers add more logic for test and debug (instead of GA filler cells), or other "non-essential" function, but such logic can be repurposed for ECOs in specific areas of the design where such ECOs are needed.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 25% of the total text.

Page 01 of 5

Enhanced metal-only ECO methodology using repurposed GA -fill-compatible non-essential logic gates


In the manufacture of CMOS VLSI chips, it is common practice to implement metal-only engineering change orders (ECOs). By limiting the changes to just the metal layers, the cost of the ECO can be minimized, since the number of new masks needed is minimized. In addition, the turn around time, from the first implementation of the change through to the point where the first hardware is available for test, is also minimized because it is possible to start with hardware that has been processed all the way up to the point of the first metal layer change, since there are no changes in the processing needed up until that point. To facilitate these metal-only ECOs, it is common practice to use gate-array-like filler cells (GA fill) which can be re-configured into useful logic gates by customizing the metal connections in an appropriate fashion, as shown in fig. 1.


Page 02 of 5

Fig. 1. GA filler cell methodology a) original GA filler cell, b) GA filler cell wired as a NAND2 gate

Variations on this methodology have been described in the past (US 20080029786A1, US 20100164547A1, or Hsien-Te Chen et al, IEEE Trans VLSI Systems, Vol 18, p. 1686 (2010), and references contained in those documents). One problem with this methodology is that the gate-array filler cells do not serve any useful purpose, unless they are used for an ECO. So the vast majority of these gate array filler cells are never employed for any functional purpose. Furthermore, the placement algorithms will tend to squeeze all the space out from regions of dense, timing-critical logic, leaving no room for gate array filler cells, and therefore no easy way to execute ECOs on that logic. Methods have been used to force open spaces for GA fill, but these can have impacts on timing and/or area. Also, once the GA cells are included in these parts of the design, there is no guarantee that it will be possible to connect any wires to them, if the wire congestion is too bad. The addition of spare logic gates is another technique commonly used to enable metal-only ECOs, but this technique is less flexible, and suffers from the same sorts of drawbacks as the GA fill methodology.

2. Summary

This basis is the realization that, in many designs, not all logic that is implemented is absolutely essential to the proper function of the hardware. If this logic is specifically marked out ahead of time, it can be implemented using "ECO gates", ie logic gates built from ECO filler cells with customized wire interconnects. If an ECO is needed, this logic can be removed from the design, and the wire interconnects re-customized to provide the function needed for the ECO instead. Equivalently, existing GA cells in the design can be used up front for extra logic used to provide increased design testability, debuggability, or increased robustness. GA filler cells can be re-purposed in this way t...