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Simple Metal ECO Methods to Bypass Power Gates for Different Failures in Power Gating Logic

IP.com Disclosure Number: IPCOM000239007D
Publication Date: 2014-Sep-30
Document File: 9 page(s) / 949K

Publishing Venue

The IP.com Prior Art Database

Abstract

Power gating is indispensable in present generation multi-core SOCs with high performance and low power requirements to reduce the standby leakage power. In newer technologies and/or newer designs, there could be failures in power gating structure. This will prevent the power gated core from either powering-up or functioning properly, which will leave the complete core untested. These failures can occur in power gate enable tree (buffer and delay logic) or in power gates. Fixing the failures of power gating logic in a conventional power grid structure requires either to overhaul the power gating structure or bypass the power gating structure. Overhaul of the power gate structure needs base layer and metal layer changes, which takes lot of effort, time, and cost to implement, which delays the silicon testing and software evaluation. This still may not ensure healthy silicon. In this paper we propose a power grid structure and a single interconnect layer ECO method for bypassing the power gating structure that enables chip testing and software evaluation to be performed.