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Test Generation technique for Validation of Microprocessor using Benchmark Speculative Flow Graphs Disclosure Number: IPCOM000239062D
Publication Date: 2014-Oct-07
Document File: 3 page(s) / 77K

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The Prior Art Database


Functional Validation plays a key role in processor development and bringup phase. Considering the tremendous growth in processors design and technology, it is becoming hard to functionally validate all the features of the microprocessor in a short time. Also the existing validation techniques like formal verification, directed testing or even the pseudo random verification process cannot ensure coverage of all possible scenarios that are encountered during actual use in customer environments. Current generation validation tools generate testcases either based on the hardware features/architecture or based on pseudo random techniques, though it helps to find lot of functional issues with the hardware the key part missing is to generate some testcases which depicts some customer workloads or benchmark patterns. The proposed solution addresses this gap by providing a methodology to solve this problem. The proposed solution captures a benchmark or a customer workload pattern and tries to generate a testcase in the framework so that the flow of testcase will give a depiction of actual workload with interesting scenarios embedded into the testcase.

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Test Generation technique for Validation of Microprocessor using Benchmark Speculative Flow Graphs

The solution provided here uses industry standard benchmarks or customer application to generate an interesting dynamic control flow graphs as a base platform to build the testcase for functional validation of the advanced microprocessor. The benchmarks are run through either a hardware platform or a simulation platform to capture the traces of instructions executed. The captured trace is processed to extract the branch instructions to build a speculation control graph out of the trace. The speculation control graph patterns are generated for many benchmarks and the each such flow graphs will be reduced to capture only the interesting and unique test scenarios from the larger flow graph. The resulting flow graphs will be stored in a repository.

This flow graphs repository is used by the test generator program to build the actual testcase which will be used to validate the functionality of the processor.

Any test generator can be used to generate interesting test instructions and data buckets to validate the microprocessor. These test instructions are embedded into each node in the speculation control graph picked by the generator module from the speculation control flow graph repository. The instructions are integrated into the control flow graph skeleton on each of the nodes and the final test program is generated.

The following flow diagram depicts the functional...