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Characterization and Parallel receiver testing of multiple lane transceivers using external loopback Disclosure Number: IPCOM000239294D
Publication Date: 2014-Oct-27

Publishing Venue

The Prior Art Database


We propose a methodology to automate test and characterize multiple lanes simultaneously on the same test bench with a focus on receiver testing such as receiver jitter tolerance, and receiver sensitivity. The methodology includes automated test and characterization of the receiver on multiple lanes, parallel testing and characterization of lanes using power splitters, and sequential testing using multiplexers on single test bench. The advantage of this method is that it allows faster time to market with maximum test coverage of transceiver or system on chip having transceiver, and saves considerable cost and time in making multiple setups.