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Off--Chip Parallel Plate Capacitor using Insulated Cu Pillars

IP.com Disclosure Number: IPCOM000239343D
Publication Date: 2014-Oct-31

Publishing Venue

The IP.com Prior Art Database

Abstract

With increased frequency of operation, SoC are facing signal and power integrity issues. To address this issue, on die decaps are used to smoothen the power lines during circuit switching. These decaps occupy precious silicon area. We propose an implementation in which these decaps are implemented off-die using copper plates that are connected to circuitry through insulated copper pillars. These decaps are suitably placed over the switching circuitry so that they are electrically very near to the circuitry.