Browse Prior Art Database

Programming and readout circuit allocation in multi-level phase-change memory array Disclosure Number: IPCOM000239473D
Publication Date: 2014-Nov-11

Publishing Venue

The Prior Art Database


Phase-change memory (PCM) is the most promising technology for future non-volatile memory chips. Memory chips based on storing a single bit of information per cells already entered the marketplace. Multiple-Level Cell (MLC) storage provides increased capacity and hence reduced cost-per-bit in memory technologies, thereby rendering such technologies suitable for big data applications. Multi-level storage requires soft information for readout and also iterative programming to store intermediate levels rendering A-to-D and D-to-A conversion necessary. Due to this fact readout and programming circuitry is nominally larger than in single-bit per cell memory types and also consumes more power. This paper presents an idea and a new conceptual implementation based on temporal and spatial sharing of readout and programming resources. The implementation allows combined 57-63% reduction in size with 55% latency penalty (or 25% latency reduction) for readout circuit and less than 5% latency penalty (or 6% latency reduction) for programming circuit.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 20% of the total text.

Page 01 of 10

Programming and readout circuit allocation in multi -level phase -change memory array

I Introduction

    Phase-change memory (PCM) has emerged as one of the most promising andidates among the emerging non-volatile memory technologies (RRAM, MRAM, FRAM, etc.) because of its speed of operation (faster than Flash memory), high throughput performance, high READ/WRITE endurance and scalability [1], [2]. PCM is the most mature technology and has already been demonstrated at the giga-bit density.

    One of the prominent features of PCM that renders it more attractive among the emerging memory technologies is its capability to store more than 1-bit per cell,
i.e. MLC storage. This is achieved by using inter-mediate resistance states for storing information, in addition to the low (SET) and high (RESET) resistance levels. MLC functionality is crucial for increasing the memory capacity and thus enhancing the cost-per-GByte competitiveness of the PCM technology. Higher densities lead to more functionality, and thus more storage as currently being demanded by big-data.

    However, MLC storage is seriously hampered by the phenomenon of resistance drift and by noise fluctuations. Drift, representing the change in resistance of the stored level over time, is one of the key challenges in the realization of MLC PCM as it limits the number of bits that can be stored in a cell. Hence, storing more than 1-bit per cell is quite challenging as conventional READ/WRITE methods are not efficient enough to successfully retrieve/store the data.

    Multi-level storage requires larger and more complex readout and programming circuitry that consumes more power compared to single-bit per cell memory types. There is an effort in MLC PCM to reduce peripheral (readout and programming) circuitry. To reduce the size and power consumption of read and programming circuitry we propose an implementation that efficiently shares common circuitry (analog front-end) between read and programming resources (spatial sharing) and blocks inside read and programming circuitry (analog front-end and A-to-D converter (ADC) in read and verifying and programming block in programming circuitry) that are not used concurrently (temporal sharing).

    The rest of the paper is organized as follows. In section II we present the principles of MLC PCM programming and readout and the sources of noise and distortion. Principle of spatial and temporal sharing of resources on the block level and system level further design improvements are described in section III. Section IV


Page 02 of 10

contains estimation of savings in area and trade-offs in increased (or reduced) latency, and section V concludes the paper.

II Principles of MLC phase-change memory

    In this section we briefly describe the principles of programming and reading of data in MLC PCM cells and memory organization.

A. Programming and reading of MLC PCM cells

PCM cells are fabricated by stacking a metal - phase change material - metal

structure on...