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High Resolution CPB Beam Methods

IP.com Disclosure Number: IPCOM000239651D
Publication Date: 2014-Nov-21
Document File: 8 page(s) / 241K

Publishing Venue

The IP.com Prior Art Database


Various techniques are described for high resolution charged particle beam processing. In-situ lamella preparation is improved using a lamella having one edge at a non-normal angle to facilitate attaching the lamella to a TEM grid in an orientation that reduces curtaining artifacts while thinning. A navigation method that does not require deprocessing uses a known offset of a region of interest from a visible feature having a known location to navigate to the region of interest. Using multiple fiducials of different sizes, each having multiple machine-recognizable elements, improves the accuracy of ion beam milling palcement. A scanning method for FIB or SEM scans different parts of a field of view at different pixel spacings, allowing a coarse image to be rapidly formed at some regions and a fine image to be formed at more interesting regions during one scan.

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Page 01 of 8

High Resolution Charged Particle Beam Methods

Thinning Methods for TEM Lamella Preparation

    When using ion beam milling for creating a flat edge, a problem called "curtaining" is often encountered. This problem occurs when the beam etches material at different rates, and deeper layers are shielded by slow-etching layers above, giving the appearance of a theater curtain. It is often desired to have the face of a sample as flat as possible, so processes for limiting these etching artifacts are desired.

    A method for preparation of TEM lamellae involves thinning the lamella from the back side of the semiconductor wafer. This method, sometimes known as inverted thinning, avoids curtaining from metal logic layers in the upper part of a cross section by etching from the bottom of the silicon substrate. However, many semiconductor manufacturers place features, often wordlines made from tungsten, below the metal gates described above. These dense features cause curtaining problems, even when etched from the back side of the wafer. One solution to this problem is simply etching with a higher ion dose. However, using a higher ion dose often requires more time for processing. Therefore, a method for quick etching without curtaining is desired.

    One process used for this procedure is to modify the best known method for inverted sample mounting so that the FIB milling is not aligned with the vertical structures typical in semiconductor devices during thinning. This markedly reduces curtaining. A method for implementation of this modification is to modify the bottom cut-out as the lamella is released from the substrate to have an angle as shown below.

Page 02 of 8

    Then the grid is oriented to the same angle as the lamella is being attached as shown below.

    In this way, the lamella edges are still aligned to the grid as if a 90 degree cut were used; however thinning can be performed at an angle to the sample structures substantially reducing curtaining artifacts.

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High Layer Defect Navigation

    Current methods for navigating to a feature of interest during examination involve manually deprocessing the entire wafer or using CAD to locate the feature. Sometimes a defect can be located by its cell address on the wafer, but this method requires deprocessing to the bit layer to count. This is time consuming, and so a better method is desired. Often, large, highly visible features are present on the sample being examined, and these can be easily located using a macro view of the sample. This method describes how a smaller feature of interest can be quickly and easily located using the known location of a reference feature. The process can be easily automated.

    If the operator has knowledge of the offset of the defect from a known visible feature, deprocessing and counting can be avoided. This enables automation to work without the use of cell counting. The coordinates of the visible feature are entered into the defect navigation file (often a "K...