Surety is performing system maintenance this weekend. Electronic date stamps on new Prior Art Database disclosures may be delayed.
Browse Prior Art Database

Assembly Register Naming for Debuggability

IP.com Disclosure Number: IPCOM000240254D
Publication Date: 2015-Jan-16
Document File: 6 page(s) / 104K

Publishing Venue

The IP.com Prior Art Database


Disclosed is a process by which a compiler augments the output (either assembler or debug listings) to print meaningful register names in assembly instructions.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 27% of the total text.

Page 01 of 6

Assembly Register Naming for Debuggability

High-level language compilers output assembly instructions that are usually not meant for humans to read . However, in some languages, it is customary to debug code by looking at the assembly created, whether it is to find bugs or analyze performance opportunities. In these instances, it is useful to provide information to the debugger (whether it is a human or a program), as part of the instructions, about what variables/symbols are located in the registers.

Current methods to improve compiler assembly listings for Reliability, Availability, and Serviceability (RAS) purposes include annotations, line numbers, various informational tables, etc. The solution disclosed herein is different from these features .

The novel contribution is a process by which a compiler augments the output (either assembler or debug listings) to print meaningful register names in assembly instructions.

Compilers generally assume an infinite number of registers when generating instructions as an intermediate step in the compilation process. This enables the compilers to separate the instruction selection and register the assignment into two separate steps . The initial registers that are used for instruction selection are virtual registers. Any given virtual register is guaranteed to use the same value as in the previous use of that virtual register. An example snippet of code appears:

Load VR123, 100(GPR5)

Load VR124, 104(GPR5)

Add VR123, VR124

Store VR123, 100(GPR5)

During register assignment, virtual registers are assigned to real registers. The VR123 is assigned to GPR1 and VR123 is assigned to GRP2. As VR123 is used in three instructions ensures the process is operating on the same value in the three instructions. It does not necessarily have to be in the same real register for every use (there could be spills, for example). Any given virtual register can hold different values, and any virtual register is not necessarily assigned to a single real register. After register assignment, virtual registers are effectively forgotten, leaving only a stream of instructions with real registers.

It is not trivial to associate the end product of instructions that use real registers with certain names . Once the compiler has the final stream of instructions, neither the origin of these instructions nor what names to give the real registers is known. The compiler has to associate the names with registers earlier in the compilation process, when it is generating instructions.


Page 02 of 6

The novel contribution is comprised of a compiler which generates instructions from internal intermediate language (IL), assuming an infinite number of registers. After all the instructions have been generated, each instruction is assigned real registers to its virtual registers. The improvement to assembly/listing annotations must be done without impact to the generated code and has to be switchable on/off (when not in RAS mode).

At a...