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Recovery of core in case of persistent cache error

IP.com Disclosure Number: IPCOM000240409D
Publication Date: 2015-Jan-29

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to mitigate the loss of a processor core due to flood of errors anywhere in its cache hierarchy. Often in an SMP, if a core conistently reports cache error, it is marked as bad. Core and caches are tightly coupled for optimal performance. This tight coupling prevents a core to function reliably. Using method below, it is possible to use this core for specific kinds of application. Once firmware error diagnosis concludes that core is faulty, it should disable that core. Hypervisor and hardware must ensure that 1. any acess to core fails gracefully. 2. all other caches in the core start acting as private cache of given core. 3. core operates on an exclusive copy of main memory. 4. core is allocated tasks which are not memory intensive.