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Automatic Sparing Operation Using Spare Row and Chipkill Disclosure Number: IPCOM000240887D
Publication Date: 2015-Mar-09
Document File: 2 page(s) / 26K

Publishing Venue

The Prior Art Database


Described is an invention that teaches automatic correction of a bad DIMM row without bringing down the system.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 100% of the total text.

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Automatic Sparing Operation Using Spare Row and Chipkill

Most systems today support "spare" operation using Spare DIMM or Spare Banks in the DIMM. DDR4 will introduce spare row in the Bank. This disclosure describes a method to use spare rows within the DDR4 Bank to perform the "DIMM spare" operation.

    DDR4 supports spare row functionality. This is a required feature for 8 Gbit, and optional for 4 Gbit. This invention describes a method of how to fix a failing DRAM (a DRAM that is causing excessive SBE) using the spare row without taking the system offline. For the purpose of this disclosure, it is assumed that the controller will continue to issue refresh cycles to memory subsystem, although it is understood that the DRAM going through the row repair will lose its data.

    When two DIMMs work in a mirroring mode, the system will switch to good DIMM in case of multibit error in one of the two DIMM. This same mechanism can be used to fix the bad DIMM and then bring back the full redundancy

    Memory controller or firmware will track number of correctable errors in different rows in a DIMM. If the number of errors in a DRAM row exceed a set limit, a spare operation will be initiated. During a DDR4 Row Repair, the specific DRAM can't do refresh, and so the data in the DRAM being repaired will be corrupted. The data in this target DRAM will get rebuilt by standard chipkill or Single Device Data Correction (SDDC) feature (see the figure below).


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