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Fine-Grid Dual-VDD Island Generation and Placement Disclosure Number: IPCOM000241053D
Publication Date: 2015-Mar-23
Document File: 4 page(s) / 247K

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The Prior Art Database


Disclosed is a two-stage flow for row based dual-Vdd island generation.

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Technology scaling has increased power density and has made power consumption a major consideration in nanometer chip designs. Because the power consumption is proportioned to the square of the supply voltage, power can be saved with lower voltage. Dual Supply Voltage (DSV) is a promising scheme to achieve power consumption reduction without degrading performance . By applying lower voltage on selected non-critical gates from a converged design, fine-grid DSV reduces power consumption while maintaining performance. However, to facilitate the power routing, it is necessary to cluster low-Vdd and high-Vdd gates to form voltage islands so that each island can reach the corresponding power line.

Figure 1: Process for Voltage Island Generation

The novel contribution is a flow to generate voltage islands by clustering gates . In literature, most works focus on creating big voltage islands; the work on fine-grid DSV is very limited. A two-stage flow is proposed for row based dual-Vdd island generation and placement. This includes:

• Max-weighted matching for latch group adjustment

• Weight based gate clustering • Min-cost max-flow for shifter assignment
• Linear programming based legalization

The goal is to create voltage islands such that VddH and VddL gates are in the VddH and VddL islands, respectively. For each VddH and VddL island, the width is no less than WVddH and WVddL , respectively. Each VddH and VddL island is a pair of mirrored row segments. Fill cells are inserted between any two adjacent VddH and

VddL islands on the same row. A le...