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Method of generating a power semiconductor device Disclosure Number: IPCOM000241403D
Publication Date: 2015-Apr-23

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The Prior Art Database

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Renato Minamisawa: AUTHOR


The present disclosure relates to a method of forming a back contact of a silicon substrate (10) of a power semiconductor device, the method comprising the steps of: a) Providing a substrate (10) at least partly formed from silicon and having a thickness of ≤ 200 µm; b) Introducing dopants (16) into the substrate (10) at a doping surface of the back side (14) of the substrate (10); c) Applying a layer comprising a metal (18) onto the doping surface; and d) Forming a metal silicide (20) from the metal (18) and the silicon of the substrate (10), wherein e) A maximum concentration of the dopant is achieved at a formed silicon/silicide interface region. Such a method provides an especially gentle and cost-saving method for heat applying joining techniques, such as die-attachment. To summarize, the present method allows forming back contacts on a silicon substrate very efficiently and with low temperatures

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Method of generating a power semiconductor device

Author: R. Minamisawa


The present disclosure relates to a method of generating a power semiconductor device. The present disclosure particularly refers to a method of of forming a back contact in a substrate of a power semiconductor device by performing a specific doping process, the method being highly effective and being capable of using low temperature techniques. The present disclosure further relates to a power semiconductor device. describes a testing method for film capacitors involving high frequency measurements. The method proposed is able to compare end-of-life behaviour of plastic encapsulated capacitors without reducing the lifetime of a good device. The advantage of the idea is a fast, cheap and non-destructive methodology which allows for an effective reliability evaluation of a batch of identical capacitors.


Thin wafer technology enables the fabrication of power semiconductor devices at low voltage rate below 1700V, where the substrate resistance dominates. In such processes, transistor structures, such as an IGBT, are processed at the top of the wafer, or at its front side, respectively, whereas a back contact is formed at the back side of the wafer, or substrate, respectively.

The main limitation of this technique can be seen in the formation of the back contact and anode region in an IGBT, for example, since the high temperature annealing generally required to activate introduced dopants damages the processed structures in the top surface, e.g. a potentially present polyimide passivation layer. Since low temperature activates few dopants, a process omitting high temperatures often results in weak anode injection efficiency for an IGBT or in high drain resistance for a MOSFET, for example.

Activation of implanted dopants by laser annealing are currently being considered as a possibility to form a high performance contact in the back side of wafers, since it delivers a high amount of heat close to the exposed back side, and thus does not damage the top side. However, this technique is very expensive due to the equipment costs as well as the frequent required exchange of the light source, which raises costs further. Also, it is not clear whether this process fulfills variability and reliability requirements.

23.04.2015 CH-14035

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23.04.2015 CH-14035

Document US 7,306,998 B2 describes a method of forming an abrupt junction device with a semiconductor substrate. In detail, said document describes to use ion implantation and siliciding for the formation of abrupt, shallow, high concentration integrated circuit source and drain junctions and thus front contacts. The method described in this document comprises the steps of providing a semiconductor substrate; forming a gate dielectric on the semiconductor substrate; forming a gate on the gate dielectric; forming a sidewall spacer on the semiconductor substr...