Stacked die on sensor die using wafer level processed spacer
Publication Date: 2015-Apr-27
The IP.com Prior Art Database
In this publication, stacking of a die on a sensor die, using wafer level processed spacers in various embodiments is disclosed. There is an ongoing demand for reduction of module costs as well as for miniaturization of sensor modules to save real estate in electronic devices. Therefore, stacking of dies within the module gains importance. When stacking dies, several constraints apply regarding size and access to the die areas needed for outside connection. For “conventional” integrated circuit dies these areas includes bond pads. In case of sensor dies, e.g. for sensing humidity, flow, pressure and/or gas, further constraints apply because a sensitive area needs access to the environment for proper sensing of the quantity to be measured. If the sensor die is smaller than a second die, stacking the sensor die on top of the second die is feasible. The second die may e.g. comprise kinds of sensors that do not need access to the environment, e.g. motion sensors, and/or ASIC. In this case, the sensor dies access to the environment can easily be assured by having the sensitive area on the free top surface of the sensor die. If the sensor die is larger than the second die, or if only the stacking of the second die on the sensor die allows for access to all needed bond pads, it may be desirable to stack the second die on the sensor die. However, this may result in blocked or limited access to the sensitive area of the sensor die. Here, we describe arrangements which allow stacking of a second die on top of a sensor die while maintaining access to the sensitive area. This is realized by introducing a spacer. We present different embodiments and a cost-effective wafer level process for the spacers.