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Wafer Level Stack Die with Flex Tape for IC Packages such as BGA, QFN, and QFP

IP.com Disclosure Number: IPCOM000241451D
Publication Date: 2015-Apr-29
Document File: 3 page(s) / 514K

Publishing Venue

The IP.com Prior Art Database


3D IC chip packaging is by stacking several silicon wafers or dies to form electrical connection vertically. This paper presents a method of silicon stacking by having flexible substrate fabricated during the wafer process level. This method eliminates the use of third party medium substrate like flexible substrate, TAB (Tape Automated Bonding). Third party medium usually is much thicker and increases the foot print of the final package. By incorporating the flex substrate at wafer level, the die to die connection can be narrower and provide a smaller footprint of the package. Saw dicing process uses two separate saw blades. The thicker saw blade to create a larger saw street to allow die flip in the next process. This stack die configuration is universal and applicable for QFN, PLCC, TSOP, QFP, BGA (MAP, TEPBGA, TBGA) packages.