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Physically Aware Clustering of Test Logic Disclosure Number: IPCOM000241504D
Publication Date: 2015-May-07
Document File: 9 page(s) / 1M

Publishing Venue

The Prior Art Database


Described is a novel method to cluster test logic in a semiconductor design to improve overall wireability and performance. A novel clustering algorithm is described as well as associated reports and visualizations to aid validation of the process.

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Physically Aware Clustering of Test Logic

In order to check the quality of a produced semiconductor, special test logic (e.g., Built-In Self-Test, OPMISR, etc.) exists in the design and can be used to share feedback on the quality of the production. This logic can feed hierarchical elements, memories, or other pieces of the design. For example, memory elements such as SRAM, RA, RF, etc., have special BIST logic. To reduce silicon area, this logic can be shared between memories of similar type (e.g., RF1 share with RF1, SRAM2 share with SRAM2, etc.). However, this sharing is typically done on a cell name basis and is, therefore, quite inefficient for the final product since it causes excessive wire. Once the memories have a physical placement, the sharing spec is manually tuned by a physical design engineer in order to produce a solution that is more wireable. If the memory placement changes, the physical design engineer may have to update the sharing spec. Additionally, the BIST logic associated with each "shared" group may be physically constrained by the physical design engineer to satisfy design requirements which could potentially lead to inferior solutions in terms of overall design wirelength and wireability.

    This idea uses a novel clustering algorithm to group elements connected to test logic to produce an optimized wirelength solution along with physical constraints, images, and reports. This approach uses heuristics and algorithms to produce such a solution that is superior to the state of the art. The proposed solution works in a general way to solve the BIST, OPMISR, and other test logic situations common on semiconductor designs. The following pseudo code describes how our idea works at a high-level:

foreach group ( get_groups() ) {
sharing = max_sharing_for_group( group ) maxdist = max_distance_for_group( group )

xy_array = find_coordinates( group )

clusters = build_clusters( xy_array, sharing, maxdist )

add_to( all_clusters, clusters ) generate_movebound( clusters )


sorted_clusters = build_daisy_chain( all_clusters )

generate_spec( sorted_clusters )

generate_cluster_visual( all_clusters )

foreach cluster ( sorted_clusters ) {
add_to( sorted_centroids, get_centroid(cluster) )

generate_daisy_chain_visual( sorted_centroids )


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build_daisy_chain ( clusters ) {
add_to( centroids, head_xy ) // (optional) if the head xy is known it helps drive the TSP solution
foreach cluster ( clusters ) {
add_to( centroids, get_centroid(cluster) )

add_to( centroids, tail_xy ) // (optional) if the tail xy is known it helps drive the TSP solution

  return TSP_solution( centroids ) }

An explanation of each subroutine follows add_to

This is just a general way to represent adding an element to a list. For example, add_to( list, a ) will add element "a" to the existing "list".


Obtain a list of elements which are to be considered part of a common group. This could be a list of memories with unique BIST logic, sub-desi...