Caching critical physical adapter state characteristics in a high-availability environment
Publication Date: 2015-May-07
The IP.com Prior Art Database
Described is a method of caching critical physical adapter state characteristics in a high-availability environment.
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Caching critical physical adapter state characteristics in a high - environment
When PCI adapters are physically separated from their PCI Express (PCIE) host bridge through PCIE re-timers, optical transceivers and their optical links as shown in Figures 1 and 2 below; it is not possible to immediately retrieve essential PCI Express status such as the current state of the link training, the current state of power, if the adapter is held in reset, and the PCI presence. In a system where the adapters are separated from the PHB, often these pieces of critical data will need to be retrieved through I2C commands to power controllers or by reading data from a controller such as an FPGA at the endpoints. This creates the problem that there are some operations that will require immediate and accurate retrieval of these values; they cannot be delayed by asynchronous operations to fetch these values. This is of particular concern when the values are retrieved by the system hypervisor during a system call from an operating system, when the duration of the call is limited, and the hypervisor cannot perform long sequences of commands with delays as an I2C communication requires. A solution must be devised that will accurately report these statuses in an immediate fashion. Furthermore, some of the states that need to be relayed to the clients are composed of data collected from multiple sources, each of which may have a delay greater than the allowable system call service time.
An alternate solution to this problem would be to just implement everything asynchronously and push the issue off to the partition. This has multiple drawbacks including that callers would need to support a busy return code, increasing their complexity. Callers would also need to wait longer during their error recovery where they make multiple fetches of the current reset state. It is also difficult to filter out transitional states that are inherent in an asynchronous architecture where timings can vary between operation or be dependent on the presence of a PCI Express Switch. An additional concern is that an existing operating system without support for busy/retry return codes can by migrated to a physical system with a newer PCIE fabric as described, and the hypervisor is required to manage this platform hardware uniqueness.
To address the problem of needing to provide correct status, but not being able to wait for the asynchronous operations to obtain this data, a cache is designed to hold the current values of this critical data. In order to provide immediate access for all interested parties, two portions of the cache exist: the first in the system call library level of the hyp...