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Layout based monte-carlo simulation with multiple integrated wafer fail checks for layout/device optimization

IP.com Disclosure Number: IPCOM000241720D
Publication Date: 2015-May-26
Document File: 3 page(s) / 79K

Publishing Venue

The IP.com Prior Art Database


Disclosed is a Monte Carlo based automated design layout optimization for multiple performance enhancements and degrade mechanisms that enables the generation of the best functional layout.

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Layout based monte-carlo simulation with multiple integrated wafer fail checks for layout/device optimization

Layout design is subjective to an individual designer, potentially allowing the generation of non-optimized designs. Design objectives need to focus on density scaling, power/performance, and yield. Designers may not be aware of different failure mechanisms and/or alternatives, and thus create a non-optimum layout that needs long turnaround time (TAT) to improve.

Wafer fail mechanisms are directly process related. Due to process variation, all failure has a failing rate. Examples of fail mechanisms include 3-sigma overlapping area for reliability, minimum insulation, and Fin end tuck-under (e.g., stitching angle and length, etc.) Based on each individual fail mechanism, the ground rule is calculated and the value is set. Each ground rule usually only involves two edges. At the layout/device level, multiple rules and fail mechanisms are involved. Often, these rules conflict, resulting in multiple fail mechanisms on the wafer; rules competing with each other leads to optimization opportunity. Especially for the most advanced technology, a smaller pitch is used to fit in everything. Single fail analysis/optimization tends to miss the cost of worsening of other failure modes.

The Current Methodology for GR Development follows:

1. Process assumptions (PA), what process can/will do
A. Process flow,
B. Patterning matrix: CD tolerance, corner rounding, etc.
C. Overlay tree

2. Ground rule (GR) calculation using Monte Carlo (MC) simulation A. Draw a simple 1D case with involving design layers (usually 2)

B. Identify the fail mechanism (new tool now offer new opportunities)

C. Derive a possible wafer contour image from design layout based on PA i. Not relying on litho simulation: too late during process cycle, too slow for MC simulation

ii.Litho simulation when available is only for sanity check

D. Overlay the wafer images of involved design layers with process variation and check the fail criteria
E. Repeat this step for MC simulation to find out failure rate at 4 sigma

GRs are ineffective in dense layout design due to generalization. For example, in the case of A/B/C/D, etc., GR always picks one value that covers all cases. GR values often have redundancy for general design and dense scaling is not a priority. GRs are usually a simplified study of one-dimensional (1D) shapes with two levels. A dense layout...