Browse Prior Art Database

Electrical failure aware verification of optical proximity correction Disclosure Number: IPCOM000241792D
Publication Date: 2015-Jun-01
Document File: 3 page(s) / 74K

Publishing Venue

The Prior Art Database


Disclosed is a method or algorithm to perform electrical failure aware optical rule checks (ORC), that includes identification off-target print image locations and modifying the input design layer by adding additional design shapes to 'mimic' print image and then perform Layout-versus-Schematic (LVS), functional/logical verification checks (on modified design layer) used upstream in tapeout process to identify electrical failures.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 51% of the total text.

Page 01 of 3

Electrical failure aware verification of optical proximity correction

1. Background and Introduction:

Optical rule checks (ORC) usually check for critical dimension (CD) variations in lithographic

print image as compared to designed target. However, as designs get denser some of these print image fails (as flagged by ORC) which may involve bridging, opens or coverage errors cannot be removed completely. Some of them have to be waived if they do not lead to 'real electrical failure'. Currently, post OPC lithographic print image checks are not aware of the underlying electrical context of error location, i.e. if certain bridge, coverage error really leads to electrical fail. For example, as seen in figure 1, via print image fail in left image doesn't cause any electrical failure as the vias belong to 'same net' (two metal lines Metal1 and Metal 2 are already shorted). However, the case on right side could cause electrical failures has the two metal lines belong to different nets and shorting of vias can lead to electrical failure. It is essential to

perform this verification before chip is fabricated. However, currently such failures are only identified in post-fabrication electrical tests and optical proximity correction (OPC) for such fail locations is fixed thereafter. This leads to significant turnaround time to reach desired yield and could cause product failures when new designs are fabricated.

Figure 1. Two cases 'Via' print image (black oval shape withcyan hash pattern) differing significantly from designed target (cyan sqaures).

2. Proposed method:

Proposed is a method to create an electrical fail aware ORC. The case of printing Sub-resolution assist feature (SRAF) has been used to describe the methodology.

The core idea of the proposed is method is as follows:

An additional shape in design layer is added at ORC error location, which is of equivalent CD as the print image at error location obtained after OPC simulations and thus the designed layer is modified. Then layout-versus-schematic (LVS) verification, functional verification, logic fail verification and parasitic extraction (PEX) etc. (all or any combination of these verifications), are performed on such a 'modified design' around the error location. Region around error


Page 02 of 3

location is so chosen as to cover all the required hierarchy levels and cells so that the verification mentioned above can be performed. If the verifications return electrical, functional or logic failures then error location is tagged as a failure site and the desig...