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An improved design methodology to achieve ground-rule clean and efficient wiring for combined packaging and chip designs. Disclosure Number: IPCOM000241929D
Publication Date: 2015-Jun-09
Document File: 5 page(s) / 215K

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The Prior Art Database


Disclosed is a new design methodology applicable to co-design, in their standard frameworks, of packaging and semiconductor process, compliant with their respective technology rules.

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An improved design methodology to achieve ground-rule clean and efficient wiring for combined packaging and chip designs.

Traditional scaling of semiconductor devices, that has been driving the semiconductor industry in the past decades (the so-called 'Moore's law') is based on reducing the necessary 2D chip footprint using more aggressive lithography. Even though this approach has been effective in the past 30 years, the lithographic equipment costs, as well as the severe process and materials limitations associated

with this aggressive scaling have forced designers to consider a parallel path to

achieve the required density and performance at the application level. One of these techniques, part of the so-called 'More than Moore' approach, that is now becoming to maturity, consists into merging the traditional packaging concepts with that of the regular silicon process, and stacking chips on top of each other, leading to the efficient use of the third dimension ( known as 2.5 or 3D integration ).

    This evolution has forced designers, that traditionally develop their circuits, simulate their electrical behaviour, and validate the resulting layout on complex Electronic Design Aids (EDA) tools, to add new stringent requirements to their design flow. They have introduced new tools and techniques to allow the co-development of a semiconductor and a packaging process.

The invention described is one of the elements of this new flow.

    The traditional EDA flows used by the industry (Cadence, Synopsys, Mentor Graphics), that have been primarily focusing on the semiconductor needs had to be updated to meet new packaging requirements.

We will present the results that we have achieved at IBM, where our Process design

Kit (PDK) flows are supported in a Cadence environment. The details of what we present is however not limited to this specific vendor, and the concepts are generic to all design databases, and EDA vendors validation tools,

    This proposal allows the designers to co-design in their standard framework packaging and semiconductor process, compliant with the technology rules, in an attempt to achieve an optimal solution within their limited development schedule.

    We propose a new pcell layout methodology applicable to an efficient and robust co-design of a packaging and of a semiconductor process. The core idea of the invention is to provide an efficient way to generate the necessary via between the semiconductor and the package, and to enhance design productivity by allowing a 'good by construction' and efficient wiring methodology. The main features and advantages of our proposal are:
- Add to a standard semiconductor PDK of all the necessary procedures supporting pcells capable to generate DRC clean complex polygons of controlled dimensions used for via in the additional packaging processes.

- Constrain the new generated shapes to make them compliant with the accepted standards and procedures used in the packaging industry (use 64 side...