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SVB Qualification Method Disclosure Number: IPCOM000241939D
Publication Date: 2015-Jun-09
Document File: 3 page(s) / 82K

Publishing Venue

The Prior Art Database


Disclosed are method and software to correct a qualification deficiency for products using Selective Voltage Binning (SVB) using a planned SVB bin adjustment to avoid design system or product redesign or re-qualification is disclosed. This method reduces qualification cost by reducing time and resource associated with redesign and re-qualification.

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SVB Qualification Method

The use of Selective Voltage Binning (SVB) in semiconductor products requires early definition of the timing voltage margin. The application of an additional guardband results in higher power and uncompetitive designs. The qualification step often identifies the need for an additional timing voltage margin beyond the original plan for the design system. Updating the library models and redesigning products can address such deficiencies; however, such updates are very costly and time consuming.

Figure 1 illustrates a process window from the fastest process to the slowest process that is allowed for shipping.

Figure 1: Selective Voltage Bins

Faster parts are run at lower voltages in systems and slower parts are run at higher voltages in systems. Figure 2 shows the relationship between the SVB bin and voltage.

Figure 2: Relationship between SVB bin and voltage

The double arrow in Figure 3 represents the amount of timing voltage margin targeted for the design system to ensure functionality at the system. Measurements are made during the qualification of a design system or individual products using SVB to ensure that a sufficient timing voltage margin is present to guarantee system performance and functionality. If the timing voltage margin is insufficient to meet qualification objectives, then the library models or chip level timing processes require updating and qualification requires repetition, which results in increased development costs and longe...